HISTORY

Tektronics, Beaverton, OR

Jan 2023 – Oct 2023

Diagnostic Network

The target system is a modular test equipment with a mainframe host and 6 slots for measuring units. I was responsible for the design of the FPGA of the mainframe which Zynq UltraScale+. The design and the verification was in SystemVerilog.
The design include AXI Intreface, PID FanController using Xilinx SYSMON4 IP and thermistors, High Resolution Timer, Interlock interface, SMBus interface, back plane FPGA interface, module FPGA interface. The verification is done using both directed testbenches for unit verification and UVM for system verification.

UVM Verification

The target design was a non-intrusive diagnostic system of distributed sensors over an ethernet network. The system is composed of a number of wired sensors for fault detection of gas turbines. The sensor is FPGA based and connected through an ethernet network.
I was responsible for bringing up the UVM verification environment and verify the functionality of the design. The system verification also includes the verification of PTP IEEE 1588 timing synchronization. The system uses both Zynq UltraScale+ and IntelFPGA Cyclone 10.

Baker Hughes, Bently, NV

Oct 2022 - Present

Smith & Nephew, Andover, MA

Nov 2020 – Sep 2022

Design and Verification

Responsible for the design and verification of endoscopy surgical imaging system, a state-of-the-art visualization platform designed for 4K imaging.
The system features a Camera Control Unit (CCU) with an integrated light source and camera head. The image and video processing was done using Xilinx Kintex Ultra Scale. The design includes 2 Microblaze soft processor cores, TEMAC Ethernet MAC/PHY, Video IP, DMA Controller, DDR3 Controller.

FPGA

Responsible for the design of a testing platform for a communications system using Xilinx Virtex Ultrascale+ and VCU118 design board
The design includes multi-core MicroBlaze, XAUI IP cores, TEMAC Ethernet core DDR4 controller, JTAG AXI Bridge and others. The design is implemented using Vivado 2018.2 and SDK. The communication system itself is implemented on multiple Microsemi RTG4 FPGAs. The debugging effort includes the use of both Vivado ILA and Microsemi/Synopsys Identify Debugger.

Northrop-Gruman, Los Angeles, CA

Dec 2020 – Aug 2021

VuSystems, Morisville, NC

Jun 2020 – Nov 2020

FPGA Lead

Architect a new FPGA system for VuSystems passive millimeter wave cameras (PMMW). This new FPGA system targets Xilinx Zynq 7020 MPSOC
. The system is divided into: PID scanner controller, image reconstruction and image processing blocks. The image processing blocks are divided between the ARM A53 embedded processor and the FPGA fabric. The interaction between the A53 and the FPGA fabric is done through the AXI bus. The PID controller and some image processing blocks are already implemented using Xilinx System Generator for DSP, Matlab and Simulink (Xilinx model-based design platform. I am also providing support for debugging their previous FPGA system which is based on Microsemi IGLOO2 FPGA.

FPGA Verification

Design and verification of the IGLOO2 FPGAs used in the auto throttle module of Boeing 737max. The job required experience with FPGA
design and verification in VHDL It also required experience in Microsemi Libero SoC 11.9 tools. It also required familiarity with DO-254 Standards and IBM Doors requirements platform

Lord Corp., Cary, NC

Jun 2019 – Apr 2020

BAE Systems, Endicott, NY

Dec 2018 – Jan 2019

FPGA Verification

Involved in the code review of three FPGAs: Xilinx and Microsemi for the flight controller of the Boeing 777x. The job required experience with FPGA
design in VHDL and Matlab/Simulink model-based FPGA design. It also required familiarity with DO-254 Standards and IBM Doors requirements platform

FPGA Verification

Design and verification of two design FPGAs: one for Microsemi IGLOO2 FPGA and another for SmartFusion2 SoC. The designs were in Verilog and the verification was carried out in SystemVerilog. The IGLOO2 design
included an arbitration of a simultaneous access of a dual-port memory (DPRAM) between a controller unit (MCU) through PCIe bus and a DSP processor through the EMIF bus. The design of SmartFusion2 included the implementation and verification of sub-nano second timestamp synchronization.

S&C Chicago, IL

May 2018 – Dec 2019

Gerber Technologies, Tolland, CT

May 2018 – Aug 2018

FPGA Verification

Design and verification of hardware debugging of a long standing problem of a controller board.
The board was based on the Microsemi ProASIC3 FPGA.

FPGA Designer

Design and verification of an AES encryption and decryption core. The core was implemented in RTL SystemVerilog.
The design targets Intel FPGA Cyclone V. The verification included timing closure at 300 MHz and hardware validation.

3DI, Inc., Apex, NC

Sep 2017 – Dec 2017

Intel, Santa Clara, CA

May 2017 - Sep 2017

SoC Protoyping

We were involved in the verification, hardware validation, and post-silicon validation of Intel GoldRidge, a 5G-baseband SoC.
The GoldRidge SoC included the ARM Coretex-A53, an ARC processor, a 5G LTE modem, PCIe, Coresight JTAG interface and DDR3 interface. The project involved the use of UVM verification as well as HW validation using Synopsys HAPS-80 FPGA-based prototyping system and Synopsys ProtoCompiler. The core of the HAPS-80 is four Xilinx Virtex UltraScale VU440. The project included the use of Synopsys VCS, Synopsys Verdi-3, Synopsys PrortoCompiler, Xilinx Vivado 2016.4, ARM DS-5 IDE. The project also included tcl sripting in Lynx operating system.

FPGA SoC Design/Verification

The task involved the design and verification of high-speed DMA access to DDR3 through AXI bus interface and low-speed DMA access to DDR3 through AHB Lite Bus interface. The design also included arbitration between the two DMA.
The task involved the design and verification of high-speed DMA access to DDR3 through AXI bus interface and low-speed DMA access to DDR3 through AHB Lite Bus interface. The design also included arbitration between the two DMA.

Metis Design Corporation, Boston, MA

May 2016 - Jan 2017

Intel, Schaumburg, IL

Aug 2015 - Jan 2016

FPGA Verification

This task involved timing closure of the different blocks of the 5G modem using Synopsys SPW, Verilog, VHDL, and SystemVerilog and Altera Arria 10 FPGA.
Intel is developing a 5G wireless baseband chipset. The system is based on LTE wireless system and is upgraded to be 10x faster (200 MHz). The system is prototyped using a board with 5 Altera Arria 10 FPGA’s. The task also included verification of the system especially high-speed serial interfaces between the 5 FPGAs. This includes Altera SerialLite III Streaming, PCIe-Avalon Bridge, and Avalon LVDS, interfaces. It also involved the use of Questa/ModelSim 10.2c, Altera Quartus II 15.0/15.1, Linux, Tcl, python, and Git.

FPGA Design In-Vehicle Infotainment

This task included the development of a testing system for Intel ValleyView II system-on-chip (SoC) for in-vehicle infotainment (IVI) system.
The task incorporated the design of different blocks that verifies the functionality of DVI video stream using CRC, audio codec, several peripheral interfaces such as SPI, I2C, LPC, SDIO, UART, DDR3 using Verilog and Xilinx Spartan 6 FPGA. The design was a multi-domain clock of a maximum frequency of 200 MHz, timing closure, Xilinx Chipsocpe ILA, and VIO, Xilinx ISE and ModelSim. We were also tasked with interfacing with the Atmel AVR 32. The task also included developing Python scripts for verifying functionality

Intel, Hillsboro, OR

Dec 2012 – Jun 2014

Microsoft, Redmond, WA

Oct 2010 – Mar 2011

FPGA Verification – Image Processing

This task involved the verification of the image and video modules implemented in Xilinx Spartan 6 to be used in Microsoft Surface
The verification methodology involved using Hardware Co-Simulation using Verilog and Xilinx System Generator and Simulink.

FPGA Design -PCIe/Multibus Bridge

I was involved in the development of bridge between PCI express (PCIe) and Multibus using Xilinx Virtex-6 FPGA using VHDL
a subcontract related to Honeywell System for the Space Station.

Tandel Systems, Oldsmar, FL

Aug 2010 – Jan 2011

Cisco Systems, Dallas, TX

Jun 2007 – Mar 2010

FPGA Design – WiMax PHY

The task involved the development of the PHY transceiver for WiMAX 802.16e using Xilinx Virtex-4 and Spartan-III FPGA’s and Altera Stratix III. The design was carried using ModelSim, Xilinx ISE, Xilinx System Generator, Altera Quartus II, and Altera System Builder.
This implementation included the development of two base stations and one Customer Premises Equipment (CPE) using VHDL and both Xilinx System Generator and Altera DSPBuilder.

FPGA Design

The task included the implemented several adaptive transmit diversity algorithms for handsets to enhance performance of 3G CDMA cellular networks using both ASICs and FPGAs.
The implementation involved several designs for voice and data standard (1x networks) as well as data only standards (1xEV-DO networks). The design included interfacing with QUALCOMM baseband processor (MSM5100) and RF vector modulator chip. Several experimental prototypes where developed to test different diversity gain algorithms. The design of the prototypes contained the interfacing with an ARM7 board and a SPI interface to a PC. The ASICs where fabricated using Jazz 0.35 BiCMOS technology. The prototypes were implemented using Xilinx Virtex II. All designs were carried out in Verilog using ModelSim for simulation, Precision RTL for synthesis, Synopsys, Primetime, Xilinx ISE for place and route, and CVS for revision control.

Magnolia Broadband, Clinton, NJ

Aug 2004 – Feb 2005

BAE Systems, Nashua, NH

Apr 2001 – 2003

FPGA Design

The task included the implementation of laser-radar (LiDAR) image reconstruction system using an array of multiple FPGAs.
The system included the development of 3D imaging system based on incoherent FM/cw ladar technology for automatic guided vehicles (AGV). This development incorporated the development of digitally controlled RF chirp generators, GaAs metal-semiconductor-metal (MSM) focal plan array (FPA), RF CMOS chip, RF SiGe chip, and mixed-signal CMOS readout integrated circuit (ROIC), and FPGA based DSP systems

HISTORY

Tektronics, Beaverton, OR

Jan 2023 – Oct 2023

Diagnostic Network

The target system is a modular test equipment with a mainframe host and 6 slots for measuring units. I was responsible for the design of the FPGA of the mainframe which Zynq UltraScale+. The design and the verification was in SystemVerilog.
The design include AXI Intreface, PID FanController using Xilinx SYSMON4 IP and thermistors, High Resolution Timer, Interlock interface, SMBus interface, back plane FPGA interface, module FPGA interface. The verification is done using both directed testbenches for unit verification and UVM for system verification.

Baker Hughes, Bently, NV

Oct 2022 - Present

UVM Verification

The target design was a non-intrusive diagnostic system of distributed sensors over an ethernet network. The system is composed of a number of wired sensors for fault detection of gas turbines. The sensor is FPGA based and connected through an ethernet network.
I was responsible for bringing up the UVM verification environment and verify the functionality of the design. The system verification also includes the verification of PTP IEEE 1588 timing synchronization. The system uses both Zynq UltraScale+ and IntelFPGA Cyclone 10.

Smith & Nephew, Andover, MA

Nov 2020 – Sep 2022

Design and Verification

Responsible for the design and verification of endoscopy surgical imaging system, a state-of-the-art visualization platform designed for 4K imaging.
The system features a Camera Control Unit (CCU) with an integrated light source and camera head. The image and video processing was done using Xilinx Kintex Ultra Scale. The design includes 2 Microblaze soft processor cores, TEMAC Ethernet MAC/PHY, Video IP, DMA Controller, DDR3 Controller.

Northrop-Gruman, Los Angeles, CA

Dec 2020 – Aug 2021

FPGA

Responsible for the design of a testing platform for a communications system using Xilinx Virtex Ultrascale+ and VCU118 design board
The design includes multi-core MicroBlaze, XAUI IP cores, TEMAC Ethernet core DDR4 controller, JTAG AXI Bridge and others. The design is implemented using Vivado 2018.2 and SDK. The communication system itself is implemented on multiple Microsemi RTG4 FPGAs. The debugging effort includes the use of both Vivado ILA and Microsemi/Synopsys Identify Debugger.

VuSystems, Morisville, NC

Jun 2020 – Nov 2020

FPGA Lead

Architect a new FPGA system for VuSystems passive millimeter wave cameras (PMMW). This new FPGA system targets Xilinx Zynq 7020 MPSOC
. The system is divided into: PID scanner controller, image reconstruction and image processing blocks. The image processing blocks are divided between the ARM A53 embedded processor and the FPGA fabric. The interaction between the A53 and the FPGA fabric is done through the AXI bus. The PID controller and some image processing blocks are already implemented using Xilinx System Generator for DSP, Matlab and Simulink (Xilinx model-based design platform. I am also providing support for debugging their previous FPGA system which is based on Microsemi IGLOO2 FPGA.

Lord Corp., Cary, NC

Jun 2019 – Apr 2020

FPGA Verification

Design and verification of the IGLOO2 FPGAs used in the auto throttle module of Boeing 737max. The job required experience with FPGA
design and verification in VHDL It also required experience in Microsemi Libero SoC 11.9 tools. It also required familiarity with DO-254 Standards and IBM Doors requirements platform

BAE Systems, Endicott, NY

Dec 2018 – Jan 2019

FPGA Verification

Involved in the code review of three FPGAs: Xilinx and Microsemi for the flight controller of the Boeing 777x. The job required experience with FPGA
design in VHDL and Matlab/Simulink model-based FPGA design. It also required familiarity with DO-254 Standards and IBM Doors requirements platform

S&C Chicago, IL

May 2018 – Dec 2019

FPGA Verification

Design and verification of two design FPGAs: one for Microsemi IGLOO2 FPGA and another for SmartFusion2 SoC. The designs were in Verilog and the verification was carried out in SystemVerilog. The IGLOO2 design
included an arbitration of a simultaneous access of a dual-port memory (DPRAM) between a controller unit (MCU) through PCIe bus and a DSP processor through the EMIF bus. The design of SmartFusion2 included the implementation and verification of sub-nano second timestamp synchronization.

Gerber Technologies, Tolland, CT

May 2018 – Aug 2018

FPGA Verification

Design and verification of hardware debugging of a long standing problem of a controller board.
The board was based on the Microsemi ProASIC3 FPGA.

3DI, Inc., Apex, NC

Sep 2017 – Dec 2017

FPGA Designer

Design and verification of an AES encryption and decryption core. The core was implemented in RTL SystemVerilog.
The design targets Intel FPGA Cyclone V. The verification included timing closure at 300 MHz and hardware validation.

Intel, Santa Clara, CA

May 2017 - Sep 2017

SoC Protoyping

We were involved in the verification, hardware validation, and post-silicon validation of Intel GoldRidge, a 5G-baseband SoC.
The GoldRidge SoC included the ARM Coretex-A53, an ARC processor, a 5G LTE modem, PCIe, Coresight JTAG interface and DDR3 interface. The project involved the use of UVM verification as well as HW validation using Synopsys HAPS-80 FPGA-based prototyping system and Synopsys ProtoCompiler. The core of the HAPS-80 is four Xilinx Virtex UltraScale VU440. The project included the use of Synopsys VCS, Synopsys Verdi-3, Synopsys PrortoCompiler, Xilinx Vivado 2016.4, ARM DS-5 IDE. The project also included tcl sripting in Lynx operating system.

Metis Design Corporation, Boston, MA

May 2016 - Jan 2017

FPGA SoC Design/Verification

The task involved the design and verification of high-speed DMA access to DDR3 through AXI bus interface and low-speed DMA access to DDR3 through AHB Lite Bus interface. The design also included arbitration between the two DMA.
The task involved the design and verification of high-speed DMA access to DDR3 through AXI bus interface and low-speed DMA access to DDR3 through AHB Lite Bus interface. The design also included arbitration between the two DMA.

Intel, Schaumburg, IL

Aug 2015 - Jan 2016

FPGA Verification

This task involved timing closure of the different blocks of the 5G modem using Synopsys SPW, Verilog, VHDL, and SystemVerilog and Altera Arria 10 FPGA.
Intel is developing a 5G wireless baseband chipset. The system is based on LTE wireless system and is upgraded to be 10x faster (200 MHz). The system is prototyped using a board with 5 Altera Arria 10 FPGA’s. The task also included verification of the system especially high-speed serial interfaces between the 5 FPGAs. This includes Altera SerialLite III Streaming, PCIe-Avalon Bridge, and Avalon LVDS, interfaces. It also involved the use of Questa/ModelSim 10.2c, Altera Quartus II 15.0/15.1, Linux, Tcl, python, and Git.

Intel, Hillsboro, OR

Dec 2012 – Jun 2014

FPGA Design In-Vehicle Infotainment

This task included the development of a testing system for Intel ValleyView II system-on-chip (SoC) for in-vehicle infotainment (IVI) system.
The task incorporated the design of different blocks that verifies the functionality of DVI video stream using CRC, audio codec, several peripheral interfaces such as SPI, I2C, LPC, SDIO, UART, DDR3 using Verilog and Xilinx Spartan 6 FPGA. The design was a multi-domain clock of a maximum frequency of 200 MHz, timing closure, Xilinx Chipsocpe ILA, and VIO, Xilinx ISE and ModelSim. We were also tasked with interfacing with the Atmel AVR 32. The task also included developing Python scripts for verifying functionality

Microsoft, Redmond, WA

Oct 2010 – Mar 2011

FPGA Verification – Image Processing

This task involved the verification of the image and video modules implemented in Xilinx Spartan 6 to be used in Microsoft Surface
The verification methodology involved using Hardware Co-Simulation using Verilog and Xilinx System Generator and Simulink.

Tandel Systems, Oldsmar, FL

Aug 2010 – Jan 2011

FPGA Design -PCIe/Multibus Bridge

I was involved in the development of bridge between PCI express (PCIe) and Multibus using Xilinx Virtex-6 FPGA using VHDL
a subcontract related to Honeywell System for the Space Station.

Cisco Systems, Dallas, TX

Jun 2007 – Mar 2010

FPGA Design – WiMax PHY

The task involved the development of the PHY transceiver for WiMAX 802.16e using Xilinx Virtex-4 and Spartan-III FPGA’s and Altera Stratix III. The design was carried using ModelSim, Xilinx ISE, Xilinx System Generator, Altera Quartus II, and Altera System Builder.
This implementation included the development of two base stations and one Customer Premises Equipment (CPE) using VHDL and both Xilinx System Generator and Altera DSPBuilder.

Magnolia Broadband, Clinton, NJ

Aug 2004 – Feb 2005

FPGA Design

The task included the implemented several adaptive transmit diversity algorithms for handsets to enhance performance of 3G CDMA cellular networks using both ASICs and FPGAs.
The implementation involved several designs for voice and data standard (1x networks) as well as data only standards (1xEV-DO networks). The design included interfacing with QUALCOMM baseband processor (MSM5100) and RF vector modulator chip. Several experimental prototypes where developed to test different diversity gain algorithms. The design of the prototypes contained the interfacing with an ARM7 board and a SPI interface to a PC. The ASICs where fabricated using Jazz 0.35 BiCMOS technology. The prototypes were implemented using Xilinx Virtex II. All designs were carried out in Verilog using ModelSim for simulation, Precision RTL for synthesis, Synopsys, Primetime, Xilinx ISE for place and route, and CVS for revision control.

BAE Systems, Nashua, NH

Apr 2001 – 2003

FPGA Design

The task included the implementation of laser-radar (LiDAR) image reconstruction system using an array of multiple FPGAs.
The system included the development of 3D imaging system based on incoherent FM/cw ladar technology for automatic guided vehicles (AGV). This development incorporated the development of digitally controlled RF chirp generators, GaAs metal-semiconductor-metal (MSM) focal plan array (FPA), RF CMOS chip, RF SiGe chip, and mixed-signal CMOS readout integrated circuit (ROIC), and FPGA based DSP systems
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