Job Description
Eximietas Design is looking for seasoned RTL Design Engineers to be part of our growing team in Austin, TX, and San Jose, CA . If you have a passion for digital design and a strong foundation in RTL coding, microarchitecture, and debugging complex IPs, we’d love to hear from you!
Job Requirements:
Title: RTL Design Engineer
Location(s): San Jose, CA/ Austin, TX
Experience: 10+ years
Must have Skills:
- Solid RTL coding experience including
- Microarchitecture of design
- System Verilog and Verilog coding using the provided coding styles.
- Understanding of SDC
- Understanding STA reports and how to adjust RTL accordingly.
- Designing for error cases and debugging IP
- Understanding of CDC logic
- Knowledge of lint rules and exceptions
- Design and use of block-level simulations to bring up IP.
- Knowledge of AMBA buses and when to use them.
Preferred Skills:
- Experience leading a small design team.
- C coding / Firmware skills
- Knowledge of common processor architectures (ARM, RiscV)
- FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.
- Lab brings up experience and scripting.
- Relevant tool experience such as: Socrates, Core Consultant in addition to standard simulation tools (xcellium, vcs, etc)
- Emulation experience (Zebu, Palladium, etc)
- Board knowledge, component selection, probing, debugging.
- JTAG debugging experience (Coresight, Lauterbach, etc).
- Low-power design techniques
Share resumes/referrals at mohini.tyagi@eximietas.design
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